Position ID US/SD/84-049-02

Timing and Device Modeling Engineer

Location: California – San Diego/San Jose, USA

Job Function
Timing verification and library modeling, CAD development and automation and low power circuit design. If you have expertise in these areas and are excited by driving leading edge semiconductor technologies to real life, this is the opportunity for you.

Key Responsibilities

• Spice circuit test bench generation, Monte Carlo spice simulations, data processing using Matlab and Perl

• Timing models validation and correlation using STA timing tools and spice simulation

• Timing corners validation using full design implementation from RTL to GDS

• AOCV table validation using spice simulation and STA tools

• CAD automation for data mining and processing

• EDA tools evaluation

• Participating in project proposal development including key milestones and deliverables

• Execute and deliver project goals in a timely manner

• Resolve issues in all phases of development to assure smooth project execution

• Conduct regular project technical review with internal and external collaborating teams on specific projects driven by the timing team

Skills & Experience 

• Advanced semiconductor device modeling and BEOL modeling - Liberty Library modeling and characterization, AOCV timing methodology, SSTA timing methodology

• Knowledge of PrimeTime, GoldTime, Design Compiler, Talus, ICC, Olympus, Cadence Virtuoso, Cadence Encounter, Matlab, StarRCXT, CalibreXRC, QRC, Hspice, Perl, Python is a plus.

• Static timing analysis tools, delay calculators, fast spice simulators

• CAD automation using: C shell, Perl, Python, Tcl/Tk, Matlab

• Circuit spice simulation and verification using: Hspice, Finesim, Spectre, BDA AFS, Cadence Oasis - Design for Manufacturing, Design for Test, Design for Yield

• Comfortable with IC design, extraction, simulation, verification tools and environments

• Excellent problem solving skills and results-driven, able to work and drive practical solutions under research environment.

• Good communication skill and personal skills in a multi-disciplinary, fast pace engineering environment

Educational Requirements
MS/PhD in Electrical Engineering or Computer Science

Position ID US/SD/85-055-98

Physical Design CAD Engineer

Location: California – San Diego/San Jose, USA

Job Function
The candidate will help develop and support the SOC physical design flow in advanced technologies such as 28nm and 20nm. This position requires in-depth understanding of the IC implementation flow from RTL to GDS2 and the challenges posed by advanced technologies in areas of Performance- Power trade-off, DFM, Advanced timing analysis and system level power integrity. The successful candidate will show detailed understanding of physical synthesis, design partitioning, floor planning, place and route, timing and power analysis required for establishing flows and methodology for physical design flow in 28nm and smaller technologies.

Key Responsibilities

• Work with physical design CAD team to develop and validate physical design flows for 28 and 20nm.

• Support ASIC physical design tools from Synopsys, Mentor and Cadence.

• Support in development of advanced power management flows (UPF implementation)

Skills & Experience

• 5 - 8 years relevant industry experience

• Expert level knowledge of floor planning, power planning, place & route, timing closure flow

• Proficient in Synopsys, Mentor or Cadence RTL2GDS2 tool set.

• Proficient in UNIX, Makefile and Tcl. Experience in PERL, HTML, C++

• Excellent interpersonal and analytical skills with the ability to work independently.

• Highly motivated, excellent team spirit, product and customer oriented.

Educational Requirements
BS/MS in Electrical Engineering or Computer Engineering

Position ID US/SD/85-054-40

Multimedia Digital Design Engineer

Location: California – San Diego/San Jose, USA

Job Function
Multimedia IP Core Front-End Digital design

Skills & Experience

• ASIC IP Core development and deployment

• Verilog/VHDL coding

• Tool: NC-SIM/Modeltech/VCS experience, Verilog/VHDL Linting, Synopsys synthesis, Formal Verification, CDC, Power Analysis

• Have owned and handled designs ~500K gates.

• Excellent communication skills

Educational Requirements
BS/MS in Electrical Engineering

Position ID US/SD/85-053-35

Validation and Integration Engineer

Location: California – San Diego/San Jose, USA

Job Function
The Validation and Integration (VI) group is responsible for verifying and validating hardware, and to integrate new hardware (IP cores and SoCs) to maximize software productivity and enable faster time to market. The VI group is central to minimizing the number of chip turns in products, to the efficient transition of sound and reliable HW to SW organizations, and to the development of new verification methodologies. Potential candidates will be developing test plan for pre-silicon or post-silicon testing, performing testing using simulation, emulation, or virtual platforms, and debugging issues in HW or SW.

Key Responsibilities
VI teams are involved across a large number of SoC products supporting a variety of wireless protocols as well as display, storage and network peripherals. VI is currently seeking self-motivated, experienced engineers with expertise in device level and system level verification, validation and debug, both in emulation and in post-Si. Applicants need to be able to design, code and test real-time embedded software to perform verification tasks for chipsets in handset and other portable target platforms.

Skills & Experience
Applicants should have 4+ years of industry experience in system integration and troubleshooting, including hands-on debugging in the lab, both on emulation platforms and on Si, working with hardware that may still be under development. Applicants should also have knowledge of real-time operating systems, and background in real-time embedded software development in C on microprocessors. Applicants should also have significant experience with one, or more, of the following:

• Diagnostic equipment such as ICE, Logic Analyzers, etc.

• High-speed buses, e.g. AHB

• Microprocessor (especially ARM) and /or DSP design and debug experience (low-level).

• Performance modeling, analysis and validation, and FPGA based emulation.

• Knowledge of several wireless standards (LTE, WCDMA, HSPA, etc.).

• Design verification, ideally using Vera or Specman.

• Familiarity with VLSI design in HDL.

Educational Requirements

BS/MS in Electrical Engineering, Electrical and computer Science Engineering, or Computer Engineering

Position ID US/SD/84-052-75

Design Verification Engineer

Location: California – San Diego/San Jose, USA

Job Function
Memory System Design Verification team is currently seeking applicants for functional design verification positions that involve the development of corresponding test plans, designing and developing verification environments, and applying these to verify complex memory hierarchy designs until coverage goals are achieved. As verification is a rapidly changing field and consumes majority of the design process, developing and deploying new verification methodologies is an essential part of the work you will do. Assertions, simulation, formal verification (static property checking), HW-SW co-verification and constraint/HVL-based verification are all tools in our verification toolbox you will use on a daily basis.

Key Responsibilities
As a Verification Engineer, you will be responsible for understanding the expected functionality of memory system designs. You will work with the architects as well as ASIC designers and SW engineers to plan and execute verification and validation of memory subsystems for integration into SoCs for mobile applications.

Skills & Experience

• Strong verification skills: test planning, problem solving, debug, adversarial testing

• DDR memory controller design/verification experience is required.

• Strong working knowledge of HVLs: SystemVerilog w/OVM, UVM

• Good written and oral communications skills required.

• Experience with simulation acceleration tool is a plus.

• Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting

Educational Requirements
BS/MS in Electrical Engineering + 10 years of experience

Position ID US/SD/83-046-48

Low Power Design Verification & Validation Engineer

Location: California – San Diego/San Jose, USA

Job Function
Design verification and post silicon validation consultants with low power design experience to work on next generation SoCs. You will be responsible for verifying and/or validating new low-power techniques and technologies in wireless communications chips and front-end design flows. In this role, the design verification engineer is responsible for the testplanning, testbench and test development, coverage closure and debugging of low power features and designs. Validation engineers will be responsible for development of testplans, tests and test code and execution, debugging, characterization and correlation of different power measures on silicon.

Key Responsibilities

• Testplanning

• Testbench and test development, coverage closure

• Debugging of low power features and designs.

• Validation engineers will be responsible for development of testplans, tests and test code and execution, debugging, characterization and correlation of different power measures on silicon.

• Be responsible for planning, tracking and managing your own tasks, deliverables to schedule and quality standards

• Understand and perform block & chip-level power analysis.

• Identify and fix any defects

• Document and support your work

Skills & Experience 

• Understanding of electrical engineering concepts, circuit analysis and logic design skills.

• Strong HVL skills, System Verilog Assertions (SVA), and System Verilog Testbench (SVTB)

• Experience with power aware simulation and static checking with UPF or CPF

• Familiarity with advanced low power techniques and high speed clocking desired.

• At least 2-5 years of experience doing low power digital ASIC design

• Programming languages: OOP, C++ VHDL, Verilog, Perl, C-shell, UNIX.

• Tool Familiarity: Modelsim, VCS, or Incisive, Debussy. Power Artist and Ptpx a plus

Educational Requirements

BS/MS/PhD in Electrical Engineering or Computer Science

Position ID US/SD/78-028-03

Functional Verification Engineer

Location: California – San Diego/San Jose, USA

Job Function
As verification is a rapidly changing field and consumes the majority of the design process, developing and deploying new verification methodologies is an essential part of the work you will do. Assertions, simulation, formal verification, HW-SW co-verification and constraint/HVL-based verification are all tools in our verification toolbox you will use on a daily basis.

Key Responsibilities
As a Functional Verification Engineer, you will be responsible for understanding the expected functionality of designs, developing corresponding test plans, designing and developing components of our verification environment, and applying these to verify complex designs until coverage goals are achieved in order to ensure the continued commercial success of our high-quality products. These designs are wireless SOCs targeted for high-performance Smartphones and Tablets.

Skills & Experience

• Strong critical thinking, problem solving and test planning skills.

• Design verification experience (developing test plan, test bench, tests, assertions, functional & code coverage, debugging tests and designs)

• General knowledge in ASIC design process, digital design, design (hw/sw) verification tools and techniques, computer architecture, etc.

• Familiar with the design, verification and assertion languages: RTL, VHDL, Verilog, System Verilog, System Verilog Assertions (SVA), Vera, e-Specman, etc.

• Knowledge of SOC, ARM processor, AMBA bus, DDR, or peripherals is preferred

• Scripting and automation skills: Unix/Linux shell programming, Perl, Makefile, revision management (e.g. CVS, ClearCase) is a plus.

Educational Requirements
BS/ MS/PhD in Electrical Engineering or equivalent technical degree; or equivalent work experience required

Position Id US/SD/67-009-81

Design Verification Engineer - CPU Team

Location: North Carolina – Cary, USA

Key Responsibilities
Implement and verify multiple complex units of a high performance low power CPU design. Responsible for logic entry, synthesis, timing analysis, test plan, test code, and design documentation. Develop, execute, and debug assembly level test programs to fully verify the function of sub-units. Work with physical design engineers, circuit design engineers, and other team members to meet all functional and performance requirements.

Skills & Experience

• Verilog or VHDL, Perl, C++, Vera/Specman, Assembly level programming.

• 3-6 Years VLSI design experience required.

• CPU design experience preferred.

• Excellent verbal and written communication skills.

• Ability to work in a team environment.

Educational Requirements
BS/MS/PhD in Electrical Engineering

Position Id US/SD/74-006-66

SoC Design Verification Engineers

Location: California - San Diego/San Jose, USA

Job Function
Candidates for functional design verification positions who will be directly involved in the verification of a variety of high-speed buses (AHB, AXI, OCP, etc.), DMA, various peripherals, security, power, memory controllers and RISC/DSP processors. As a Functional Verification Engineer, you will be responsible for understanding the expected functionality of designs, developing corresponding test plans, designing and developing components of our verification environment, and applying these to verify complex designs until coverage goals are achieved in order to insure the continued commercial success of our high-quality products.

Skills & Experience

• Strong critical thinking, problem solving and test planning skills.

• General knowledge in ASIC design process, digital design, design (hw/sw) verification tools and techniques, computer architecture, etc.

• Requires a minimum of 4+ years industry experience.

• Familiar with the design and assertion languages: RTL, SystemVerilog, SystemVerilog Assertions (SVA), Vera, e-Specman, VHDL, Verilog, PSL, etc.

• Scripting and automation skills: Unix/Linux shell programming, Perl, Java, Makefile, XML, XML DOM, XPath, XSLT, revision management (e.g. Clearcase, CVS, & DesignSync) is a plus.

• Knowledge of wireless/wired communications and protocols or graphics/video multi-media is helpful, as are good written and oral communications skills.

Key Responsibilities
As verification is a rapidly changing field and consumes the majority of the design process, developing and deploying new verification methodologies is an essential part of the work you will do. Assertions, simulation, formal verification, HW-SW co-verification and constraint/HVL-based verification are all tools in our verification toolbox you will use on a daily basis.

Educational Requirements
BS/MS/PhD in Electrical Engineering or equivalent preferred.

Position Id US/SD/74-005-87

Multimedia Design Verification Engineer

Location: California - San Diego, USA

Key Responsibilities
As a Verification Engineer, you will be responsible for understanding the expected functionality of multimedia designs, specifically video processing hardware subsystems. You will work with the architects of these multimedia systems, as well as multimedia ASIC designers and SW engineers to plan and execute verification and validation of multimedia subsystems for integration into SoCs for mobile applications.

Skills & Experience

• Strong verification skills: test planning, problem solving, debug, adversarial testing.

• Multimedia video (MPEG-2/4, H.264, VP6/7/8, DIVX and VC1) or graphics (OPEN-GL/CL, DX-9/10/11) hardware experience is preferred.

• Strong working knowledge of HVLs: System Verilog, VERA/e-Specman, System C

• Experience with methodologies like OVM and UVM.

• RTL design experience and/or very strong OO programming experience is also a plus.

• Good written and oral communications skills required.

• Experience with simulation acceleration tool is a plus.

• Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting.

Educational Requirements
BS/MS/PhD in Electrical Engineering or Computer Science

Position ID US/SD/83-047-49

Low Power Design Engineer

Location: California – San Diego/ Texas - Austin, USA

Job Function
Design consultants with low power design experience to work on next generation SoCs. You will be responsible for integrating new low-power techniques and technologies in wireless communications chips and front-end design flows. In this role, the design engineer is responsible for the design and integration of low power IP and technologies including design, specification, RTL coding, simulation, synthesis, etc

Key Responsibilities

• Apply new low-power technologies to new and existing designs

• Perform RTL design, simulation, synthesis, and timing analysis.

• Be responsible for planning, tracking and managing your own tasks, deliverables to schedule and quality standards

• Understand and perform block & chip-level power analysis.

• Identify and fix any defects

• Document and support your work

Skills & Experience 

• Understanding of electrical engineering concepts, circuit analysis and logic design skills.

• Familiarity with advanced low power techniques and high speed clocking desired.

• At least 2-5 years of experience doing low power digital ASIC design

• Programming languages: VHDL, Verilog, Perl, C, C++, C-shell, UNIX.

• RTL design skills – RTL coding, simulation, synthesis DFP and understanding of timing and physical design.

• Tool Familiarity: Modelsim, VCS, or Incisive, Debussy, Spyglass, PowerArtist, Synopsys DC, PrimeTime, PTPX.
  

Educational Requirements

BS/MS/PhD in Electrical Engineering or Computer Science

Position ID US/SD/82-042-97

Digital Design Engineer

Location: California – San Diego/San Jose, USA

Job Function
Module level digital design and implementation including rtl, linting, cdc, synthesis, sta.

Skills & Experience

• Minimum of 5-7 years of digital ASIC design experience including Verilog coding, linting, synthesis, formal verification (LEC), and Static Timing Analysis

• Specific experience with Spyglass, Zero-in, Conformal LEC, and Conformal LP is desired

• Experience with audio signal processing is a plus

Educational Requirements

BS/MS in Electrical Engineering or equivalent experience

Position ID US/SD/82-040-26

High Speed Digital Designer

Location: California – San Diego/San Jose, USA

Job Function
Help with tool flows for RTL code quality checking (linting, reset, low power, dft) and delivery of high speed cores that can scale up to 1Ghz speeds.

Skills & Experience

• At least 10 years of industry experience

• Hardware Design and VLSI Design industry experience in RTL Design implementation and Digital Design.

• Must have significant expertise on Design Compiler and Primetime.

• Should have had significant exposure and close interaction with Physical Design Teams and in performing timing related ECO's and working on physical placement aspects.

Educational Requirements
BS/MS in Electrical Engineering/Computer Science

Position ID US/SD/81-035-08

ASIC Digital Design Engineer

Location: California – San Diego/San Jose, USA

Job Function
Module level digital design including RTL, Linting and CDC

Skills & Experience

• Minimum of 5-7 years of digital ASIC design experience including Verilog coding, linting, synthesis, formal verification (LEC), and Static Timing Analysis.

• Specific experience with Spyglass, Zero-in, Conformal LEC, Conformal LP, and Tetramax are a plus.

• Experience with low-power high-volume products is desired

Educational Requirements

BS/ MS in Electrical Engineering, or equivalent professional experience

Position ID US/SD/77-027-76

Design Engineer

Location: California – San Diego/San Jose, USA

Skills & Experience

• Detailed knowledge of ASIC design including architecture, verification of integrated systems, RTL design, synthesis, and timing closure

• Specific experience with Synopsys DC/PC, LINT, PTSI, and Verilog/VHDL is required

• Experience with VLSI designs targeting 45nm or below preferred

Educational Requirements

BS/ MS/PhD in Electrical Engineering or equivalent technical degree; or equivalent work experience required

Position ID US/SD/83-043-21

Physical Design Engineer

Location: California - San Diego/San Jose, USA

Job Function
Candidate should have at least 8-15 years of relevant. Candidate must be able to deal with MSM Top level complexity from Placement, CTS, Routing and timing closure.

Skills & Experience

• Proficient in timing closure, constraints, SI prevention/fixing, Clk synthesis, power planning

• Expert in Synopsys ICC, Magma Talus, Mentor Olympus, Cadence FE tool set.

• Experience in Mentor caliber tools to run Physical verification

• Knowledge of I/R drop analysis is a Plus

• Excellent interpersonal and analytical skills with the ability to work independently.

• Highly motivated, excellent team spirit, product and customer oriented.

• Experience in Tcl/Tk, PERL is a Plus

Educational Requirements

BS/MS in Electrical Engineering or Computer Science

Position ID US/SD/82-041-93

Senior DFT Methodology Engineer

Location: California – San Diego/San Jose, USA

Job Function
Digital ASIC Design Team is currently seeking candidates for a senior position responsible for the development of advanced DFT/DFD(design for test/design for debug) techniques for low power, high performance and highly integrated SoCs including RF, CODEC, power management devices and high-speed PHY & SerDes systems. The successful candidate will help to develop DFT methodologies that reduce test cost, increase production quality and enhance yield learning, as well as work with implementation teams to productize the DFT/DFD features and provide training to DFT design and test engineering communities on DFT/DFD techniques.

Key Responsibilities

• Develop and standardize advanced DFT methodologies to reduce test costs and increase production quality.

• Drive DFT test strategy definition and validation, coverage analysis and improvement, and verification flows.

• Work with DFT designers to implement, verify, and productize DFT/DFD features.

• Provide training to DFT design and test engineering communities on advanced DFT/DFD techniques.

• Participate in 3rd party IP evaluation, acquisition and deployment.

• Interact with internal and external cross-functional groups to determine and fulfill design automation needs.

Skills & Experience
Required Experience:

• Strong fundamental knowledge of DFT/DFD techniques for high performance processors.

• Understanding of core-based test methodology and scan isolation.

• Knowledge in fault modeling Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and other advanced DFT models.

• Knowledge in JTAG, MBIST, Scan Compression, ATPG, Fault Simulation and at-speed testing.

• Experience with industry ATPG tools Synopsys Tetramax, Cadence Encounter Test or Mentor Fastscan ATPG tools.

• Synopsys DFTC scan insertion.

• Experience in Logic Design, VHDL, Verilog RTL, verification, and static timing analysis.

• Working knowledge in one or more of the following; C, C++, TCL or Perl.

• Experience with industry simulation tools such as VCS, Modelsim, or others.

• Direct experience in silicon bring-up, debug, and validation of DFT features on ATE.

• Detail oriented with strong organizational, problem solving and communication skills.

Desired Experience:

• Experience and understanding of Analog, Mixed Signal, High Speed I/O, PLL and Custom Test methodologies and techniques including Analog BIST, Loopback test, Eye test, Analog performance measurement techniques, etc.

• Experience in design and verification of the above; layout, SPICE simulation, etc.

• Experience with formal verification tools such Verplex, Formality, etc.

• Knowledge and experience of timing closure and industry tools like PrimeTime and PTSI.

• Experience with other industry tools such as Vera, Spyglass, 0-in, Jasper, RedHawk, PrimePower.

Educational Requirements

MS/PhD in Electrical Engineering

Position Id US/SD/76-010-36

Board Design Engineer

Location: California - San Diego, USA

Skills & Experience

• At least two year hands-on CCA design experience with focus on digital and analog circuit design.

• Proficiency with mentor CCA design flow, schematic entry, layout etc.

• Experience with lab test equipment (logic analyzer, oscilloscope), board bring-up experience required.

• Perl scripting skills required.

• Documentation skills required.

• Must work on site.

• Good verbal and written communication skills.

Nice to have:

• Experience with FPGA design (Xilinx EDK) a plus.

• Experience with simulation tools for FPGA a plus.

Educational Requirements

BS/MS/PhD in Electrical Engineering