Design Verification Engineer

Req ID :          IN/207/DV

Location :       Bangalore

Experience :   3 to 10 years

Qualification : BE or ME / MTech / MS in EE, ECE, Electrical

Job Description:   

 - Expertise in System Verilog with one or more methodologies (OVM / UVM / VMM) is MUST

 - Experience in deploying constraint random and assertion based verification environments

 - Strong domain knowledge on one or more - PCIe,USB, Ethernet, ARM, AHB/AXI, AMBA

 - Should have worked on SOC verification on at least one project with constrained random    methodology (eRM/VMM/OVM)

 - Working knowledge of building verification env, writing and debugging test cases, coverage analysis (Code , Functional)

 - Expertise in Verilog, VHDL, C++, Vera, e, System C is PLUS

 - Scripting using Tcl /Perl/Shell a plus

Design Engineer

Req ID :          IN/72/SYNTH & STA

Location :       Bangalore

Experience :   2 to 8 years

Qualification : BE or ME / MTech / MS in EE, ECE, Electrical

Job Description:

 - Hands on experience in Synthesis and STA for Full Chip and Core level

 - Experience in setting up full chip synthesis flow and develop synthesis constraint

 - Experience timing closure activities and coming up with STA constraints for the design

 - Experience with Synopsis Design Compiler (DC), PrimeTime (PT) and PrimeTime Signal Integrity ( PT-SI)  tools is required

 - Experience with Cadence RC and ETS is a preferred

 - Should have good knowledge on Design architecture, RTL, Netlist and DFT methodology

 - Should be able to write simple scripts to process the timing reports, generate timing and functional (ECO)

 - Worked on latest technology nodes

 - Should understand Physical Design flow and able to provide inputs for implementation

 - Should have timing closure experience for at least 2 full chips SOC designs

Req ID :          IN/117/PD

Location :       Bangalore

Experience :   2 to 8 years

Qualification : BE or ME / MTech / MS in EE, ECE, Electrical

Job Description:

 - Experience in cutting edge technology nodes ( 28nm, 45nm and 65nm)

 - Hands on experience in Top/Block level floor planning, power planning, IR drop analysis, Timing closure with Xtalk and OCV

 - Worked on Multimode multi corner optimization, Clock tree synthesis and advanced clock tree implementation

 - Experience in Top/Block level timing closure with sign off STA, Scan chain reordering, Top/Block level ECO implementation involving netlist level logical changes

 - Excellent debugging skills in implementation issues and ability to come up with creative solutions

 - Worked on Library performance analysis and fine tuning for implementation

 - Exposure to designs critical for power, area and timing at the same time.

 - In depth Implementation exposure in one or more platforms (Magma/Encounter/Mentor/Synopsys/Atoptech).

 - Worked on sign off  tools (DRC/LVS/PT)

 - Scripting experience in Perl/TCL is MUST

DFT Engineer

Req ID :          IN/115/DFT

Location :       Bangalore

Experience :   2 to 6 years

Qualification : BE or ME / MTech / MS in EE, ECE, Electrical

Job Description:

 - Strong knowledge in all aspects of the DFT domain i.e. concept to DFT implementation, ATE applications

 - Experience with ATPG modeling and verification

 - Hands-on experience with DFT compiler, DFT max and TetraMAX

 - Hands-on experience on Test mode controllers, scan insertion and verification, Memory BIST insertion and verification and JTAG